1.
Prasanth Varasala, Babulu Karapa, Kamaraju Maddu. Intelligent Clock Gating for FPGA-based RISC Architectures: A Novel Approach to Switching Activity and Dynamic Power Reduction. IJC. 2024;51(1):79-89. Accessed April 29, 2026. https://ijcjournal.org/InternationalJournalOfComputer/article/view/2238