Intelligent Clock Gating for FPGA-based RISC Architectures: A Novel Approach to Switching Activity and Dynamic Power Reduction

Abstract

In modern digital systems, dynamic power consumption remains a critical concern, particularly in Field-Programmable Gate Arrays (FPGAs) utilized in power-sensitive applications. This paper presents a novel intelligent clock gating technique specifically tailored for FPGA-based RISC architectures to effectively reduce switching activity and dynamic power dissipation. Our approach leverages a combination of hardware and software strategies to dynamically control the clock signals to inactive modules, thereby minimizing unnecessary power consumption. The proposed method integrates seamlessly with existing FPGA design flows and RISC architectures, providing a scalable and efficient solution for power management. Through comprehensive simulations and experimental evaluations on standard benchmark circuits, we demonstrate a significant reduction in dynamic power consumption while maintaining performance and functionality. At higher frequencies overall 64% power on total power is saved.