Hybrid Domino XOR Gate with Dual Threshold Voltage Transistors

Authors

  • Milad Alizadeh Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran
  • Mozhgan Golzani Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran
  • Mohammad Poliki Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran

Keywords:

low power, domino XOR gate, evaluation phase, precharge phase.

Abstract

At the present time, in integrated circuit technology CMOS, low power design is an important subject in system design. In order to achieve this target, power consumption must be minimized. In this article two new domino XOR gates in 45nm technology are presented. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. By eliminating two input inverter and preventing the pulse flow to the output node during the precharge phase, power consumption in this circuit is reduced. First proposed circuit reduces active mode power consumption by  78.91% and 54.55% as compared to standard N-type domino XOR and P-type domino XOR.. Similarly, second proposed circuit reduces active mode power consumption by 81.43% and 59.98% as compared to standard N-type domino XOR and P-type domino XOR.

References

Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits- Analysis and Design, 3rd ed., Tata Mc Graw-Hill ed., pp. 115-129, 211-214, 2003.

A. Bellaouar and M. I. Elmasry, “Low-power Digital VLSI Design: Circuits and Systems”, Kluwer Academic Publishers, 2nd ed, 1995.

C. Cornelius, S. Koppe and D. Timmermann, "Dynamic Circuit Techniques in Deep Submicron Technologies: Domino Logic reconsidered," 2006 IEEE International Conference on IC Design and Technology, Padova, 2006, pp. 1-4.

P. K. Verma, S. K. Singh, A. Kumar and S. Singh “Design and Analysis of Logic Gates Using Static and Domino Logic Technique”, International Journal of Scientific & Technology Research, June 2012, Vol. 1, No. 5, pp. 122-125.

M. Kishor and J. P. Gyvez, “Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families”, IEEE, 2000, pp. 349-357.

S. Jia, S. Lyu, Q. Meng, F. Wu and H. Xu, “A New Low-Power CMOS Dynamic Logic Circuit”, IEEE conference on EDDSSC, 2013, Hong Kong.

H. F. Dadgour and K. Banerjee, “A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic OR Gates”, IEEE Trans. on VLSI Systems, Nov. 2010, Vol. 18, No. 11, pp. 1567-1577.

Dicleli M, Bruneau M. Seismic performance of single-span simply supported and continuous slab-on-girder steel highway bridges. Journal of Structural Engineering, ASCE; 121(10): 1497-1506, 1995.

ASHTO. LRFD bridge design specifications (4th ed.). Washington (DC): American Association of State Highway and Transportation Officials; 2007.

Chopra AK. Dynamics of structures: Theory and applications to earthquake engineering (2nd ed.), Prentice Hall, Englewood Cliffs, 2001.

Computers and Structures, Inc. SAP2000, version 7.4, Integrated structural analysis and design software. Berkeley, CA; 2000.

Nowka .K. J and Galambos .T (1998), “Circuit design techniques for a gigahertz integer microprocessor”, IEEE International Conference on Computer Design,pp.11-16.

Neil H.E. Weste, David Harris,Principles of CMOS VLSI Design: A System Perspective,(3rd ed.)Addison-Wesley (2004).

Tyler Thorp, Dean Liu, PradeepTrivedi,Analysis of blocking dynamic circuits,IEEE Transactions on VLSI Systems (2003), pp. 744-749.

Kumar, Sujeet, et al. "Design and simulation of low power dynamic logic circuit using footed diode domino logic." Engineering and Systems (SCES), 2013 Students Conference on. IEEE, 2013.‏

Downloads

Additional Files

Published

2018-02-07

How to Cite

Alizadeh, M., Golzani, M., & Poliki, M. (2018). Hybrid Domino XOR Gate with Dual Threshold Voltage Transistors. International Journal of Computer (IJC), 28(1), 90–100. Retrieved from https://ijcjournal.org/index.php/InternationalJournalOfComputer/article/view/1089

Issue

Section

Articles