A New Reversible Design of Adder & Subtractor Using Reversible Logic Gates

  • Sonawane Swati Shrinivas ME ( E & T C ) Dept JSPM’s BSIOTR, Wagholi, Pune, India
  • Proff. Vishal Puranik (E & TC) Dept JSPM’s BSIOTR Wagholi, Pune, India
Keywords: Fredkin Gate, Constant Inputs, Garbage Output.


Modern VLSI design circuitry is used for low power consumption which is the requirements of ICs. Reversible logic has its tremendous applications and importance because it doesn’t lose any single bit of information of no information while performing computation bit loss during computation; it reflects the result in low power dissipation. However, we have to convert the reversible circuits into fault tolerant reversible circuits; it helps to detect the occurrence of errors and faults. Parity preserving property can be used for this. A new parity preserving reversible gate is proposed in this paper, named as P2RG. The most significant aspect of this work is that it can work as a full adder as well as full subtractor by using one P2RG and Fredkin gate only. This proposed design is very good in terms of gate count, garbage outputs, constant inputs and area than the existing similitude. The concept behind the reversible logic circuits is that the inputs and outputs are same.


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How to Cite
Shrinivas, S. S., & Puranik, P. V. (2018). A New Reversible Design of Adder & Subtractor Using Reversible Logic Gates. International Journal of Computer (IJC), 30(1), 1-5. Retrieved from https://ijcjournal.org/index.php/InternationalJournalOfComputer/article/view/1231